A NOVEL ARCHITECTURE FOR OPTIMIZED FIR FILTER BASED ON 16-BIT APPROXIMATE MULTIPLIER

Abstract

FIR filter is valuable in numerous applications, for example, present day signal handling and correspondence frameworks. In this paper an enhanced FIR filter planned by utilizing 16X16 approximate multiplier dependent on parallel prefix adder is proposed. This proposed 16X16 approximate multiplier structured with four 8X8 approximate multipliers, three parallel prefix adder [PPA] and one OR gate. The parallel prefix adder give the less insertion delay, this prompts increment in the superior for the count in the less time. The 8X8 multiplier structured utilizing approximate tree compressor [ATC] and carry maskable adder [CMA]. The proposed multiplier is compared and a regular Wallace tree multiplier diminished basic way delay by 10%. This proposed multiplier improves the execution of the FIR filter. It is executed in Xilinx ISE version 14.7.

Keywords: Approximate multiplier, Parallel prefix adder, Brent-kung adder, FIR filter, Serial adder, incomplete adder cell.